A problem commonly associated with MOS and CMOS ramdom access memories (herein called RAMs) is substrate noise caused by capacitive coupling of the RAM's bit lines with the substrate (or the p- or n- well in the case of CMOS RAMs) during the sensing cycle. This substrate noise problem is often compensated for in prior art devices by slowing down the sensing cycle. In the present invention this problem is totally eliminated by a design which results in balanced, and thus self-cancelling, capacitive coupling of the bit lines to the substrate.
The prior art also includes a growing number of CMOS pseudostatic dynamic RAMs which are designed to mimic some of the operating characteristics of static RAMs.
As is well known, conventional dynamic RAMs are less convenient to use than static RAMs because: (1) special care must be taken by the user to ensure that all the cells of the dynamic RAM are refreshed periodically; and (2) dynamic RAMs typically have complicated timing requirements whereas static RAMs typically are relatively simple to use. A number of prior art devices have includes auto refresh circuitry which makes the device self refreshing. The present invention greatly simplifies the timing requirements for using a dynamic RAM and thus addresses the other one of the two major difficulties associated with the use of dynamic memories. In particular, the present invention provides a dynamic memory wherein bit line precharge is performed at the beginning of each access cycle, rather than between access cycles. Therefore the access and cycle times of the memory are equal, and the user of the memory need not provide for a precharge period between memory access cycles.
The combination of the precharge and sensing features of the present invention enables the construction of CMOS dynamic RAMs which are faster and easier to use than the prior art devices known to the inventors.
It is therefore a primary object of the present invention to provide an improved dynamic random access memory.
Another object of the present invention is to provide a CMOS dynamic RAM which uses balanced bit line sensing to substantially eliminate substrate noise during the sensing cycle.
Still another object of the present invention is to provide a CMOS dynamic RAM with equal access and cycle time.